1. Field of the Invention
The present invention relates to a memory device, or apparatus capable of being applied to, for instance, an image data memory.
2. Description of the Prior Art
A dual port video RAM (random access memory) with such a structure as shown in FIG. 1 has been utilized as the conventional memory device (apparatus) 1 used in the image data process.
In this memory device 1, there are provided 16 (4.times.4) memory cells R00 to R33 at cross positions between, for instance, 4 word lines L0, L1, L2, and L3 and 4 bit lines L10, L11, L12, L13. Also, an upper 2-bit word addressing address signal 51 among a 4-bit address signal is supplied to 2-bit input terminals A0 and A1 of an address decoder DEC 1 used to connect outputs QA, QB, QC and QD to these word lines L0, L1, L2, L3, so that a designation is made of the word lines L0, L1, L2, L3 via the address decoder DEC 1, and memory cell rows (R00-R03), (R10-R13), (R20-R23), (R30-R33) for 4 lines connected to the respective word lines can be accessed.
The bit lines L10, L11, L12, L13 are connected respectively to the first memory cell (R00, R10, R20, R30), the second memory cell (R01, R11, R21, R31), the third memory cell (R02, R12, R22, R32), and the fourth memory cell (R03, R13, R23, R33) of the memory cell rows (R00-R03), (R10-R13), (R20-R23), (R30-R33), and furthermore via a buffer amplifier circuit AMPI to a 4-bit output register REG1. As a result, at the timing when a load signal S2 is supplied to a load terminal LD of the output register REG1, 4-bit memory data stored in the memory cells constituting the memory cell rows connected to the word lines designated by the address decoder DEC1 are stored into this output register REG1.
The memory data of the output register REG1 become outputs A, B, C, D of a selecting output circuit SELl including switching transistors TR1, TR2, TR3, TR4 which receive the bit outputs QA, QB, QC, QD of an output decoder DEC2 as open control signals, and then are sent out to an output line OUT 1 as serial output data S3.
To the 2-bit input terminals A0, A1 of the output decoder DEC2, outputs QB and QA of a bit address counter CNTRI are supplied. As a result, the counting operation of this bit address counter CNTR1 is performed as 1 period for a 4-bit address signal in response to a clock signal S4 supplied to a clock input terminal CLK based on a lower 2-bit bit-addressing address signal 55 among the 4-bit address signal furnished to the load input terminals B and A. Then, the 4 outputs A, B, C, D of the selecting output circuit SELl are sequentially sent out as output data S3 based on a head bit address designated by the bit-addressing address signal S5.
The load signal S2 for the output register REG1 is generated from a load control circuit CONT1 in synchronism with the output operation explained above.
In the arrangement of the conventional memory device shown in FIG. 1, image data for 1 line (namely, 4 bits image data) has been written by a separate write circuit (not shown) in the memory cells R00-R33 in such a manner that these memory cells occupy a single word line, or occupy two adjoining word lines.
If, for instance, image data for b 1 line is written into the memory cells in such a manner that the memory cell R00 is used as the head address for this 1-line image data, this 1 line image data is written into the memory cells (R00, R01, R02, R03). This 1-line image data does not bridge, or ride, memory cell rows for two word lines.
However, if the 1-line image data is written such that the memory cell R02 is used as the head address, this 1-line image data is written into the memory cells bridging the memory cell rows (R02, R03, R10, R11) of two word lines.
According to the arrangement of the conventional memory device shown in FIG. 1, when the 1-line image data is stored into the memory cells R00-R33 bridging the memory cell rows for two word lines, such a cumbersome memory operation must be carried out whereby after an n-th word line connected to the memory cell for the head address has been selected by the address decoder DEC1, an (n+1)th word line must subsequently be designated by the address decoder DEC1 at a predetermined timing. As a consequence, the address decoder DEC1 and the related peripheral circuitry may become complex.